Field of the Invention
The invention relates to a touch sensitive housing, and more particularly to a method of making a touch sensitive housing formed with touch sensor pads, each containing an active metal layer and a metal layer formed on the active metal layer.
Description of the Related Art
U.S. Pat. No. 7,656,393 discloses a touch sensitive housing or bezel that includes a housing wall and a touch sensitive surface integrated into the housing wall. The touch sensitive surface has a capacitive sensor array and a data acquisition circuitry having a configuration similar to those disclosed in U.S. patent application Ser. No. 10/949,060. Conventionally, such capacitive sensor array is formed by forming a metal layer on a substrate through metallization or metal deposition, followed by patterning the metal layer through photolithographic and etching techniques. However, it is relatively difficult to form circuits on a curved and bent wall surface.
Electroless plating of metal to form circuit patterns on insulating substrates, such as formation of conductive lines on a circuit board, has been known in the art. U.S. Pat. No. 4,898,648 discloses a conventional method of forming a circuit pattern on an insulating substrate involves the steps of forming an active metal layer on an insulating substrate, laser patterning the active metal layer to form a pattern of active metal lines, followed by electroless plating of conductive metal lines on the active metal lines of the patterned active metal layer. However, the circuit pattern thus formed has a relatively low adherence to the insulating substrate. U.S. Pat. No. 4,898,648 also discloses an improved method of making a circuit pattern on a circuit board. FIGS. 1A to 1D illustrate consecutive steps of the improved method. The method includes forming an active metal layer 92 on a circuit board 91, electroless depositing a deposited metal layer 93 on the active metal layer 92, laser patterning the deposited metal layer 93 and the active metal layer 92 to form the deposited metal layer 93 into metal lines 931 and the active metal layer 92 into metal lines 921, and electroplating a plated metal layer 94 on the metal lines 931, thereby forming the circuit pattern on the circuit board 91.
The aforementioned method is disadvantageous in that since the ablated portions of the deposited metal layer 93 and the active metal layer 92 removed by the laser ablation has a relatively large area comparing to those of the metal lines 931 or the metal lines 921, the method is time consuming and has a high power consumption and a tendency of massively damaging the insulating substrate.